A 20 K GaAs array with 10 K of embedded SRAM

A 20000-gate GaAs array with 10 K of embedded RAM is presented. The array contains eight scannable fully registered 256×256 RAM macros which have a minimum cycle time of 3.5 ns. The RAM features a scan mode, which can be used to configure the registers into a serial shifter. There is also a RAM test mode which allows independent functional and speed testing of all eight RAMs, easing the task of RAM verification for a given user personalization. The RAM array was fabricated using an advanced high-performance GaAs semiconductor E /D MESFET process featuring self-aligned gates and requiring only 12 masks. Introductory discussion of the Vitesse GaAs process, basic GaAs MESFET characteristics, and GaAs circuit design are provided. The gate array portion contains 20736 user-configurable cells with 10-ps gate delays which are tailored for direct-coupled FET logic (DCFL). The I/O can be personalized for ECL, TTL, or GaAs levels. There are 392 pads on the 13.8-mm×7.7-mm die with a maximum of 256 used for signal I/O. The RAM array is packaged in a multilayer ceramic 344-pin leaded chip carrier (LDCC). Typical power dissipation at 80% utilization is 14 W