Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard

This work presents a cost function optimization for the internal decision of the HEVC Sample Adaptive Offset (SAO) filter. The optimization approach is focused on an efficient hardware design implementation, and explores two critical points. The first one focus in the use of fixed-point data instead of float-point data, and the second focus on reduce the number of full multipliers and divisors. The simulations results show that those proposals do not present significant impact on BD-rate measurements. Based on both these two hardware-friendly optimizations, we propose a hardware design for this cost function module. The FPGA synthesis results show that the proposed architecture achieved 521 MHz, and are able to process UHD 8K@120 fps operating at 47 MHz.