Title :
A 0.8-μm advanced single-poly BiCMOS technology for high-density and high-performance applications
Author :
Iranmanesh, Ali A. ; Ilderem, Vida ; Biswal, Madan ; Bastani, Bami
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
3/1/1991 12:00:00 AM
Abstract :
A single-poly, 0.8-μm advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process
Keywords :
BIMOS integrated circuits; application specific integrated circuits; emitter-coupled logic; integrated circuit technology; integrated memory circuits; logic arrays; 0.8 micron; ABiC IV; ASIC; ECL gate arrays; ECL memory; W plugs; advanced polysilicon technology; application-specific IC; bipolar transistors; digital IC; double-diffused bipolar process; embedded CMOS; emitter-coupled logic; four level metallisation; high-density; high-performance CMOS; high-performance applications; low encroachment recessed oxide isolation; silicided local interconnection; single-poly BiCMOS technology; twin buried layers; Application specific integrated circuits; BiCMOS integrated circuits; Bipolar transistors; CMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Logic arrays; Metallization; Standards development;
Journal_Title :
Solid-State Circuits, IEEE Journal of
