Title :
Josephson macrocell array
Author :
Kotani, Seigo ; Inoue, Atsuki ; Hasuo, Shinya
Author_Institution :
Fujitsu Lab. Ltd., Atsugi, Japan
fDate :
4/1/1991 12:00:00 AM
Abstract :
A modified variable-threshold logic (MVTL) gate for use in Josephson LSI circuits is considered. A 7.6 K-gate Josephison macrocell array whose functions can be changed by wiring changing has been developed. Automatic design problems, such as AC powering and small fan-outs, are solved by constructing the macrocell with a three-phase powering system and developing a magnetically coupled unit cell. The chip contains 21440 Josephson junctions on a 5 mm×5 mm die and is fabricated using 1.5 μm all-niobium Josephson techniques. An average delay of 5.3 ps/gate in the macrocell and a total chip power consumption of 23 mW have been obtained
Keywords :
Josephson effect; large scale integration; logic arrays; logic gates; superconducting junction devices; superconducting logic circuits; 1.5 micron; 23 mW; 5.3 ps; Josephson LSI circuits; Josephson junctions; Josephson macrocell array; MVTL gate; Nb; magnetically coupled unit cell; modified variable-threshold logic; three-phase powering system; Circuits; Delay; Josephson junctions; Large scale integration; Macrocell networks; Semiconductor devices; Superconducting devices; Superconducting magnets; Voltage control; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
