Title :
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
Author :
Yang, Chih-Kong Ken ; Horowitz, Mark A.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
12/1/1996 12:00:00 AM
Abstract :
A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-μm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3× oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3×3 mm2
Keywords :
CMOS digital integrated circuits; data communication; data communication equipment; demultiplexing; digital communication; multiplexing; transceivers; 0.8 micron; 2.488 Gbit/s; CMOS process; OC-48 serial data links; clock recovery; high-speed serial data; multiple phased clocks; oversampling receiver; oversampling transmitter; receiving front-end circuit; transceiver; Bandwidth; CMOS process; CMOS technology; Clocks; Demultiplexing; Frequency; Phase locked loops; Phase noise; Sampling methods; Transmitters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
