Title :
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs
Author :
Jozwik, Krzysztof ; Tomiyama, Hiroyuki ; Edahiro, Masato ; Honda, Shinya ; Takada, Hiroaki
Author_Institution :
Grad. Sch. of Inf. Sci., Nagoya Univ., Nagoya, Japan
fDate :
6/1/2012 12:00:00 AM
Abstract :
Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.
Keywords :
field programmable gate arrays; logic testing; reconfigurable architectures; virtualisation; CPU accelerators; FPGA area utilization; Virtex-4 FPGA; Xilinx; audio processing HW tasks; cryptographic HW tasks; dynamic properties; image processing HW tasks; memory protection; memory virtualization; partially reconfigurable FPGA; preemption schemes; preemption techniques; static properties; system responsiveness; Clocks; Digital signal processing; Field programmable gate arrays; Hardware; Multiplexing; Random access memory; Registers; Dynamic reconfiguration; FPGA; runtime reconfiguration;
Journal_Title :
Embedded Systems Letters, IEEE
DOI :
10.1109/LES.2012.2193660
