• DocumentCode
    1491228
  • Title

    30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

  • Author

    Anghel, Costin ; Hraziia ; Gupta, Anju ; Amara, Amara ; Vladimirescu, Andrei

  • Author_Institution
    Inst. Super. d´´Electron. de Paris, Paris, France
  • Volume
    58
  • Issue
    6
  • fYear
    2011
  • fDate
    6/1/2011 12:00:00 AM
  • Firstpage
    1649
  • Lastpage
    1654
  • Abstract
    This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the ION current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the ION current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate.
  • Keywords
    field effect transistors; tunnel transistors; TFET; ambipolar current; optimization; size 30 nm; tunnel FET; tunnel field-effect transistors; CMOS integrated circuits; Doping; Logic gates; Performance evaluation; Silicon; Transistors; Tunneling; Ambipolar current; low-$k$ spacer; tunnel field-effect transistor (TFET); tunneling;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2011.2128320
  • Filename
    5746513
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1491228