• DocumentCode
    1491604
  • Title

    SOI and bulk CMOS frequency dividers operating above 15 GHz

  • Author

    Floyd, B.A. ; Shi, L. ; Taur, Y. ; Lagnado, I. ; O, K.K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
  • Volume
    37
  • Issue
    10
  • fYear
    2001
  • fDate
    5/10/2001 12:00:00 AM
  • Firstpage
    617
  • Lastpage
    618
  • Abstract
    Dual-phase dynamic pseudo-NMOS ([DP]2) frequency dividers have been implemented in a partially scaled 0.1 μm CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]2 latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V
  • Keywords
    CMOS logic circuits; delays; frequency dividers; silicon-on-insulator; 0.1 micron; 1.5 V; 13.3 ps; 13.5 mW; 15.4 GHz; 16.2 ps; 18.75 GHz; 9.8 mW; SOI; bulk CMOS; dual-phase dynamic pseudo-NMOS; frequency dividers; latch delays; partially scaled CMOS technology; power consumption; speed;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010446
  • Filename
    923967
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1491604