The charge-transfer feedback-controlled split-path CMOS buffer

Author

Cheng, Kuo-Hsing ; Yang, Wei-Bin ; Huang, Hong-Yi

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

Volume

46

Issue

3

fYear

1999

fDate

3/1/1999 12:00:00 AM

Firstpage

346

Lastpage

348

Abstract

A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the short circuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper buffer at 100 MHz operation frequency

Keywords

CMOS digital integrated circuits; buffer circuits; circuit feedback; high-speed integrated circuits; low-power electronics; 100 MHz; HSPICE simulation; MOS transistors; charge-transfer buffer; charge-transfer diodes; feedback-controlled split-path method; high-speed CMOS buffer; low-power CMOS buffer; output inverter; power dissipation; power-delay product; propagation delay; short circuit current elimination; CMOS technology; Circuits; Diodes; Energy consumption; Frequency; Inverters; MOSFETs; Power dissipation; Propagation delay; Signal design;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.754867

Filename

754867