Abstract :
A VLSI coprocessor that radically improves the real-time performance of the Ada tasking model, especially the rendezvous, is discussed. An overview of multilevel design is given, and design levels and models are examined. A description is given of the design strategy, which entails stepwise refinement of functional models representing the coprocessor at more and more detailed levels. A chip was generated using the Genesil silicon compiler, but most of the design was defined and verified on the instruction-set-processor and register-transfer levels.<>
Keywords :
Ada; VLSI; circuit layout CAD; Ada tasking; Genesil silicon compiler; VLSI coprocessor; functional models; instruction-set-processor; multilevel design; real-time coprocessor; real-time performance; register-transfer levels; stepwise refinement; Algorithms; Application software; Computer architecture; Coprocessors; Costs; Operating systems; Program processors; Real time systems; Silicon; Very large scale integration;