Integer-N PLLs Verification Methodology: Large Signal Steady State and Noise Analysis

The need for accurate and fast verification of the phase locked loop (PLL) circuits is a designers´ important concern before the chip tape-out. This paper covers two major PLL characteristics for circuit verification: steady-state response and phase noise. A new simulation methodology is proposed and comprehensively described. It is general purpose and can be implemented within the framework of all commercial radio frequency integrated circuit (RFIC) simulation tools. By using the new algorithm, we succeed in predicting integer-N PLL´s characteristics with the same precision as the conventional brute-force transistor-level simulation while spending much less time and computer memory. It is composed of two stages, a hierarchical analysis algorithm for the steady state response calculation and a bottom-up behavioral modeling strategy for the phase noise analysis that accurately accounts for the non-idealities in all PLL blocks.