The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates.<>