System-Level ESD Protection Design Using On-Wafer Characterization and Transient Simulations

Author

Scholz, Matthias ; Shih-Hung Chen ; Thijs, Steven ; Linten, D. ; Hellings, Geert ; Vandersteen, Gerd ; Sawada, Masanori ; Groeseneken, Guido

Author_Institution

IMEC, Leuven, Belgium

Volume

14

Issue

1

fYear

2014

fDate

Mar-14

Firstpage

104

Lastpage

111

Abstract

A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built.

Keywords

electrostatic discharge; integrated circuit packaging; integrated circuit reliability; IC packaging; circuit design; component-level ESD protection design; off-chip protection device; on-wafer characterization; system-level ESD protection design; system-level ESD stress; system-level electrostatic discharge stress; transient simulation; Clamps; Electrostatic discharges; Hidden Markov models; Integrated circuit modeling; Stress; Testing; Transient analysis; Electrostatic discharge (ESD); integrated circuit (IC) reliability; reliability; system analysis and design;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2012.2201720

Filename

6208850