• DocumentCode
    1497071
  • Title

    Bulldozer: An Approach to Multithreaded Compute Performance

  • Author

    Butler, Michael ; Barnes, Leslie ; Sarma, Debjit Das ; Gelinas, Bob

  • Author_Institution
    Adv. Micro Devices, Sunnyvale, CA, USA
  • Volume
    31
  • Issue
    2
  • fYear
    2011
  • Firstpage
    6
  • Lastpage
    15
  • Abstract
    AMD bulldozer module represents a new direction in microarchitecture and includes a number of firsts for AMD, including AMD multithreaded X86 processor, implementation of a shared level 2 cache, and X86 processor to incorporate floating-point multiply-accumulate (FMAC). This article discusses the module multithreading architecture, power-efficient micro architecture, and subblocks, including the various microarchitectural latencies, bandwidths, and structure sizes.
  • Keywords
    floating point arithmetic; instruction sets; microprocessor chips; multi-threading; parallel architectures; Bulldozer module; X86 processor; floating-point multiply accumulate; microarchitecture; multithreaded architecture; Bandwidth; Decoding; Hardware; Instruction sets; Multithreading; Pipeline processing; Throughput; Bulldozer; Microprocessors; microarchitecture implementation considerations; microcomputers; processor architectures;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2011.23
  • Filename
    5751937
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1497071