• DocumentCode
    1497574
  • Title

    A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost

  • Author

    Chen, Zhen ; Xiang, Dong

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • Volume
    29
  • Issue
    6
  • fYear
    2010
  • fDate
    6/1/2010 12:00:00 AM
  • Firstpage
    966
  • Lastpage
    976
  • Abstract
    This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most influence on fault coverage. The conflict-driven selection method selects some flip-flops that work in the enhanced scan mode or skewed-load scan mode. And the conflict-driven reordering method distributes the selected flip-flops into different chains. In the multiple scan chain architecture, to avoid too many scan-in pins, some chains are driven by the same scan-in pin to construct a tree-based architecture. Based on the architecture, the new test application scheme allows some flip-flops to work in enhanced scan or skewed-load mode, while most of others to work in the traditional broadside scan mode. With the efficient conflict-driven selection and reordering schemes, fault coverage is improved greatly, which can also reduce test application time and test data volume. Experimental results show that fault coverage based on the proposed method is comparable that of enhanced scan.
  • Keywords
    automatic test pattern generation; fault simulation; flip-flops; integrated circuit testing; trees (mathematics); automatic test pattern generation; conflict-driven reordering method; flip-flops; hybrid scan testing; selection and reordering schemes; transition fault coverage; Automatic generation control; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Delay; Flip-flops; Pattern analysis; Test pattern generators; Broadside testing; fault coverage; hybrid scan testing; test cost;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2010.2048359
  • Filename
    5467329