Title :
Automating Logic Transformations With Approximate SPFDs
Author :
Yang, Yu-Shen ; Sinha, Subarna ; Veneris, Andreas ; Brayton, Robert K.
Author_Institution :
Vennsa Technol., Toronto, ON, Canada
fDate :
5/1/2011 12:00:00 AM
Abstract :
During the very large scale integration design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate sets of pairs of functions to be distinguished and avoid the memory/time explosion issue inherent with the original representation. Then, it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.
Keywords :
VLSI; circuit optimisation; combinational circuits; integrated circuit design; logic design; sequential circuits; combinational design; data structure; logic structural transformation; memory-time explosion; sequential design; simulation-based formulation; very large scale integration design; Computational modeling; Data structures; Dictionaries; Integrated circuit modeling; Mathematical model; Sequential circuits; Wire; Correction; SPFD; debug; engineering change; logic restructuring; logic rewire; optimization; very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2011.2110590