Compensation Design for DC Blocking Multilayer Ceramic Capacitor in High-Speed Applications

The shunt parasitic capacitance of a multilayer ceramic capacitor (MLCC) mounting structure seriously degrades the performance of the MLCC in high-speed applications. In this paper, we propose a new compensation design method with which the reference planes underneath the surface mount technology pads and MLCC are cleared to eliminate the excessive capacitance effect. An analytical model is derived to compute the optimal clear parameters using conformal mapping, and the result of the analytical model closely matches with that of Ansoft 2-D Extractor. It is convenient for the printed circuit board (PCB) designer to utilize this model to obtain the optimal compensation parameters without building the 2-D or 3-D models of the MLCC mounting structure. Simulation and measurement results show that the compensation design is effective in improving the signal integrity of dc blocking MLCCs mounted on high-speed PCBs.