DocumentCode :
1498743
Title :
Stacking chips in 3D
Volume :
26
Issue :
5
fYear :
2009
Firstpage :
2
Lastpage :
2
Abstract :
3D IC solutions have been developed for several different reasons: to reduce the system form factor for portable platforms; to increase system performance by alleviating the interconnect-delay bottleneck; and to manage overall system cost by stacking heterogeneous chips, rather than integrate diverse system components into a single chip through 2D scaling. However, although some 3D IC markets are emerging, and most technical issues of 3D integration are almost solved, several thermal and production-test challenges remain as obstacles. This special issue of IEEE Design & Test takes a look a those issues.
Keywords :
Costs; Hardware; Production; Propulsion; Research and development; Semiconductor device measurement; Semiconductor device testing; Stacking; System performance; Three-dimensional integrated circuits; 3D IC design and test; integration; interconnect-delay bottleneck;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2009.122
Filename :
5286141
Link To Document :
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