Title :
Multidimensional Test Escape Rate Modeling
Author :
Butler, Kenneth M. ; Carulli, John M., Jr. ; Saxena, Jayashree ; Nahar, Amit ; Daasch, W. Robert
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
Today´s SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.
Keywords :
integrated circuit testing; system-on-chip; IC products test coverage; SoC design; rate prediction; Circuit testing; Design for testability; Electronic equipment testing; Instruments; Integrated circuit modeling; Integrated circuit testing; Multidimensional systems; Production; Semiconductor device testing; Test pattern generators; Defect level; defective parts per million (DPPM); design and test; fault coverage; test escapes; yield;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.118
