Title :
Robust On-Chip Signaling by Staggered and Twisted Bundle
Author :
Yu, Hao ; He, Lei ; Chang, Mau-Chung Frank
Author_Institution :
Nanyang Technol. Univ., Singapore, Singapore
Abstract :
Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25times compared to designs employing coplanar shields.
Keywords :
crosstalk; integrated circuit interconnections; multiprocessor interconnection networks; chip multiprocessor interconnects; delay variation; inductive return path; on-chip signaling; shield insertion; staggered bundle; twisted bundle; Clocks; Coupling circuits; Crosstalk; Delay; Integrated circuit interconnections; Logic circuits; Robustness; Signal design; Switches; Testing; chip multiprocessors; crosstalk reduction; interconnect structure; on-chip signaling; shield insertion;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.121
