A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Author

Farjad-Rad, Ramin ; Yang, Chih-Kong Ken ; Horowitz, Mark A. ; Lee, Thomas H.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

580

Lastpage

585

Abstract

A serial link transmitter fabricated in a large-scale integrated 0.4-μm CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5×2.0 mm² of die area

Keywords

CMOS integrated circuits; VLSI; coaxial cables; intersymbol interference; large scale integration; pulse amplitude modulation; telecommunication signalling; 0.4 micron; 1 W; 10 Gbit/s; 10 m; 200 to 350 mV; 3.3 V; 4-PAM pre-emphasis serial link transmitter; 90 to 100 ps; channel low-pass effects; clock frequency; coaxial cable; data eye opening; intersymbol interference; large-scale integration; multilevel signaling; process-limited on-chip frequency; symbol rate; three-tap pre-emphasis filter; transmitter output driver; CMOS process; Clocks; Copper; Filters; Frequency; Intersymbol interference; Large scale integration; Multiplexing; Signal processing; Transmitters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760366

Filename

760366