Design and simulation of power efficient traffic light controller (PTLC)

This paper presents design and simulation of a power efficient traffic light controller (PTLC). The main focus is on simulation and optimization of PTLC design and computing its speed of operation. In the conventional system, power consumption is high and expensive. The design of PTLC is better than conventional in terms of LUT´s (number of gates), complexity, size and cost. In this research paper a novel PTLC is presented with a minimum number of LEDs which fairly improves its performance and makes the design efficient in terms of power and speed with respect to conventional design. The conventional traffic light controller has been implemented using microcontroller and FPGA´s. The research paper by Parasmani in 2013 stated the use of FPGA to design an advanced traffic light controller which uses the sensor to maintain the continuous traffic flow hence the power consumption is too high which can be reduced by the design PTLC. The novel design of PTLC is an economical and possess the characters of high integration, low power and flexibility. The PTLC has been implemented using FPGA. FPGA has many advantages as the speed, number of input/output ports and performance. This system has been successful tested and implemented in hardware using Xilinx v 10.1 software packages using Very High Speed Integrated circuit hardware description language (VHDL), RTL and technology schematic are included to validate simulation results.