Effect of temperature and chiral vector on emerging CNTFET device

Author

Sinha, Sujeet Kumar ; Singh, Prashant ; Chaudhury, Santanu

Author_Institution

Dept. of Electr. Eng., NIT Silchar, Silchar, India

fYear

2014

fDate

5-7 March 2014

Firstpage

432

Lastpage

435

Abstract

In this paper we have analyzed the merits of CNTFET devices over MOSFET in nanoscale regime, by comparing the effect of oxide thickness on quantum capacitance. After this we have observed and analyzed the effect of variation of chiral vector and temperature on threshold voltage of CNTFET device. After simulation on HSPICE tool we can conclude that for high threshold voltage as required for low leakage in nanoscaled devices, chiral vector (m,n) should be relatively small. We have further analyzed the effect of temperature on threshold voltage in CNTFET devices and is found to be negligibly small. There is a little variation in the threshold voltage for both positive and negative temperatures.

Keywords

capacitance; carbon nanotube field effect transistors; chirality; nanoelectronics; semiconductor device models; C; CNTFET devices; HSPICE simulation; carbon-nanotube field effect transistor; chiral vector; oxide thickness; quantum capacitance; temperature effect; CNTFETs; Logic gates; MOSFET; Quantum capacitance; Threshold voltage; Vectors; CNTFET; MOSFET; chiral vector; chirality; oxide thickness; quantum capacitance; temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing for Sustainable Global Development (INDIACom), 2014 International Conference on

Conference_Location

New Delhi

Print_ISBN

978-93-80544-10-6

Type

conf

DOI

10.1109/IndiaCom.2014.6828174

Filename

6828174