Improved dual second-order generalized integrator PLL for grid synchronization under non-ideal grid voltages including DC offset

This paper presents an improved dual second-order generalized integrator phase-locked loop (DSOGI-PLL) for three-phase systems, for dealing with the non-ideal three-phase grid voltages (e.g. unbalance, harmonics, frequency variation, magnitude variation, etc.) and rejecting the error caused by the DC offset introduced by signal conditioning and A/D conversion in practice, the SOGI used in the proposed PLL was improved by adding the third integrator to generate a state variable which will be equal to the DC component of the input signal, and then the state variable is subtracted from the input signal to reject the DC offset. Extending this improvement to three-phase systems, the dual SOGIs employed in the standard DSOGI-PLLs was replaced by the dual improved SOGIs. The complexity of the PLL is almost the same as the standard DSOGI-PLL, but the performances are enhanced. Simulation and experimental results show that the proposed improved DSOGI-PLL is correct, effective and feasible.