A reduced switching loss PWM strategy to eliminate common mode voltage in multilevel inverters

This paper introduces a novel PWM technique to eliminate common mode voltage (CMV) in multilevel inverters using the three zero common mode vectors. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process, as a switching time diagram and switching state sequence, can be fully explored in that active inverter. Due to the existence of an unequal number of commutations of three-phases in each sampling period, the optimization of the switching loss is achieved by a proposed current mapping algorithm. The switching loss reduction can be up to 25% as compared to the same PWM technique with non-optimized algorithms. The theoretical analysis is verified by simulation and experimental results.