Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

This paper presents a technique for achieving reduced input current ripple in multi-phase power converters that provide multiple heterogeneous power rails, such as that present in portable electronics or computers. Through asymmetric interleaving of individual phases, the input current ripple of the power converter can be reduced compared to conventional, symmetric interleaving. We analyze the practical implementation challenges in a digital control implementation, and provide simulation and experimental results that quantify the performance improvement possible through our proposed technique. We demonstrate close to a 3× reduction in input current ripple through the use of the proposed technique, compared to conventional methods, using a micro-controller that controls a multi-phase 180 nm CMOS power management IC system.