DocumentCode
1503385
Title
Ultrathin stacked Si3N4/SiO2 gate dielectrics prepared by rapid thermal processing
Author
Ting, Wei-Yuan ; Ahn, J.H. ; Kwong, D.L.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
27
Issue
12
fYear
1991
fDate
6/6/1991 12:00:00 AM
Firstpage
1046
Lastpage
1047
Abstract
Ultrathin (58 AA equivalent oxide thickness) stacked Si3N4/SiO2 (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O2 and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO2 and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flat-band voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.
Keywords
CVD coatings; dielectric thin films; electric breakdown of solids; electron traps; leakage currents; metal-insulator-semiconductor structures; oxidation; silicon compounds; 58 AA; CVD; MNOS devices; O 2; RTO; Si 3N 4-SiO 2-Si; charge trapping; chemical vapour deposition; flat-band voltage instability; leakage current; low-defect property; low-field breakdown events; nitride thickness; rapid thermal oxidation; rapid thermal processing; stacked gate dielectrics; ultrathin dielectrics;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19910650
Filename
76184
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