Implementation of LVRT techniques of grid-connected PCS with the adaptive low pass notch PLL method

This paper proposes a fault ride-through (FRT) techniques based on low-pass notch filter PLL (LPN-PLL). The proposed LPN-PLL is an upgraded version of fast Fourier transform PLL (FFT-PLL) which is robust to the harmonics and imbalance of the grid voltage and is based on the fast Fourier transform (FFT) concept instead of using a conventional synchronous reference frame PLL (SRF-PLL), which requires a d-q axis transformation of three phase voltage and proportional-integral (PI) controller. The proposed phase locked loop (PLL) algorithm and FRT control strategy was implemented digitally using a digital signal processing (DSP) TMS320F28335. Three phase grid-connected inverter (10kW) and prototype voltage sag generator (10kVA) are set and a verification experiment is performed to show the high performance and robustness of the proposal under low voltage ride-through (LVRT) operation.