Junctionless Vertical-Si-Nanowire-Channel-Based SONOS Memory With 2-Bit Storage per Cell

Author

Sun, Y. ; Yu, H.Y. ; Singh, N. ; Leong, K.C. ; Lo, G.Q. ; Kwong, D.L.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

Volume

32

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

725

Lastpage

727

Abstract

This letter reports on a junctionless silicon/oxide/nitride/oxide/silicon memory realized on vertical-Si-nanowire gate-all-around structures with two physical storage nodes per cell. Two physical bits per cell are electrically evaluated by studying the second bit effect and the program/erase speeds, endurance, and retention. The relaxed channel length limitation due to the vertical structure provides more tolerance to overcome the scaling-related reliability issues. In addition, the absence of junctions reduces the process complexity and cost, thus making this device more manufacturable with a very low thermal budget.

Keywords

integrated circuit reliability; integrated memory circuits; nanowires; silicon; Si; channel length limitation; junctionless vertical-Si-nanowire-channel-based SONOS memory; physical storage nodes; process complexity; program-erase speeds; scaling-related reliability; second bit effect; thermal budget; word length 2 bit; Junctions; Logic gates; SONOS devices; Silicon; Sun; Wire; Gate-all-around (GAA); junctionless (JL); multibit storage; vertical silicon nanowire (SiNW);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2131118

Filename

5756454