Title :
Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs
Author :
Chen, C.K. ; Chen, C.L. ; Gouker, P.M. ; Wyatt, P.W. ; Yost, D.-R. ; Burns, J.A. ; Suntharalingam, V. ; Fritze, M. ; Keast, C.L.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
fDate :
7/1/2001 12:00:00 AM
Abstract :
We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured.
Keywords :
CMOS integrated circuits; MOSFET; circuit stability; delays; photolithography; silicon-on-insulator; 0.5 V; 248 nm; 90 nm; SLOTFETs; Si; bias voltage; fully depleted SOI CMOS; locally thinned SOI channel; low-resistance T-shaped polysilicon gate; nitride spacer technology; optical lithography; raised source-drain regions; ring-oscillator propagation delay; sacrificial layer; self-aligned devices; CMOS process; CMOS technology; Etching; High speed optical techniques; Implants; Lithography; MOSFETs; Optical device fabrication; Silicon on insulator technology; Space technology;
Journal_Title :
Electron Device Letters, IEEE
