DocumentCode :
1506610
Title :
A reconfigurable multifunction computing cache architecture
Author :
Kim, Huesung ; Somani, Arun K. ; Tyagi, Akhilesh
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume :
9
Issue :
4
fYear :
2001
Firstpage :
509
Lastpage :
523
Abstract :
A considerable portion of a microprocessor chip is dedicated to cache memory. However, not all applications need all the cache storage all the time, especially the computing bandwidth-limited applications. In addition, some applications have large embedded computations with a regular structure. Such applications may be able to use additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. Thus, we propose adaptive balanced computing (ABC)-dynamic resource configuration on demand from application-between memory and computing resources. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations: finite impulse response and discrete/inverse discrete cosine transform. In order to convert a cache memory to a function unit, we include additional logic to embed multibit output lookup tables into the cache structure. The experimental results show that the reconfigurable module improves the execution time of applications with a large number of data elements by a factor as high as 50 and 60.
Keywords :
FIR filters; cache storage; discrete cosine transforms; microprocessor chips; reconfigurable architectures; adaptive balanced computing; cache memory; discrete cosine transform; dynamic resource configuration; finite impulse response; inverse discrete cosine transform; microprocessor chip; reconfigurable multifunction computing cache architecture; Cache memory; Computer applications; Computer architecture; Coprocessors; Field programmable gate arrays; Hardware; Programmable logic arrays; Programmable logic devices; Reconfigurable logic; Table lookup;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.931228
Filename :
931228
Link To Document :
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