Title :
A 90-nm CMOS multi-standard GNSS receiver front-end
Author :
Chi-Wei Cheng ; Chen, Yi-Jan Emery
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A receiver architecture aiming to receive the L1-band multi-standard Global Navigation Satellite System signals simultaneously is described in this paper. In the proposed receiver, the GPS/Galileo and GLONASS signals are treated as the unwanted image signals for each other, and rejected for the respective down-conversion outputs. The receiver was implemented in TSMC 90-nm CMOS process and achieves more than 20 dB image reject ratio. Without an additional receiver chain, this architecture provides the benefits of low cost and power consumption. The total power consumption of the receiver frontend is 15.79 mW with a 1-V power supply, and the die area is 1.536 mm2.
Keywords :
CMOS integrated circuits; UHF integrated circuits; field effect MMIC; radio receivers; satellite navigation; CMOS multistandard GNSS receiver front-end; GLONASS signal; GPS signal; Galileo signal; Global Navigation Satellite System; L1-band receiver architecture; power 15.79 mW; size 90 nm; unwanted image signal; voltage 1 V; Amplitude modulation; CMOS integrated circuits; Frequency synthesizers; Gain; Global Positioning System; Mixers; Receivers; GLONASS; GNSS; GPS; multi-standard; receiver;
Conference_Titel :
Silicon Monolithic Integrated Circuits in Rf Systems (SiRF), 2014 IEEE 14th Topical Meeting on
Conference_Location :
Newport Beach, CA
DOI :
10.1109/SiRF.2014.6828511