Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a high-rate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation.