Towards asynchronous power management

Power management is an important part of modern microelectronics, however, the possibilities for its design automation are insufficiently studied and therefore the state-of-the-art synthesis methods produce suboptimal power control circuits. Currently the same design principles, which are based on synthesis of synchronous state machines, are used for both the data processing components and the power control circuits. While the synchronous operation is natural for data processing, it does not meet the low-latency and resilience requirements imposed by the power control logic. We believe that design of power control requires a fundamentally different approach based on clock-less design principles, which are characterised by robust operation in variable conditions and high responsiveness to the input stimuli. One of the main obstacles on this pathway is the difficulty of expressing the intended power control behaviour in a formal and unambiguous form which can be subsequently used for logic synthesis and verification of the obtained solution.