Performance analysis of single stage interconnection networks

Author

Burke, J. Richard ; Chen, Chienhua ; Lee, Tsung-Ying ; Agrawal, Dharma P.

Author_Institution

Semicond. Res. Corp., Research Triangle Park, NC, USA

Volume

40

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

357

Lastpage

365

Abstract

A single-stage interconnection network (SSIN) consisting of only one stage of switches and recirculation through processors is studied. An analytical probability model for SSINs using 2×2 switches is introduced, and results obtained with the model are compared with simulation results. Four SSINs with different network sizes, loading, and routing strategies are discussed. Processors with and without buffers are considered, and three different routing strategies are applied to resolve conflicts. The analytical model is seen to be in close agreement with the simulation results while providing at least an order of magnitude reduction in CPU time

Keywords

multiprocessor interconnection networks; performance evaluation; queueing theory; CPU time; analytical probability model; buffers; conflict resolution; loading; performance analysis; processors; recirculation; routing; simulation; single stage interconnection networks; switches; Analytical models; Communication switching; Costs; Hardware; Multiprocessor interconnection networks; Network topology; Performance analysis; Queueing analysis; Routing; Switches;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.76415

Filename

76415