Analysis and design of fast settling voltage-controlled delay line with dual-input interpolating delay cells

An analysis of the delay characteristic of a voltage-controlled delay line (VCDL) exploiting a dual-input interpolating delay cell is presented and a design technique to incorporate the VCDL for a multiphase delay-locked loop is proposed. A recurrence relation of delay time of each delay cell in the VCDL and its closed-form expression show that the delay of each delay cell converges to a specific value with an error-decaying rate which depends on the weight of interpolation. A weight-adjusted delay cell is inserted to reduce the initial error and thereby the delay of the following delay cell converges fast. The validity of the analysis and the feasibility of the proposed scheme are verified by circuit simulation.