Chaotic neuron models and their VLSI circuit implementations

Author

Hsu, Charles C. ; Gobovic, Desa ; Zaghloul, Mona E. ; Szu, Harold H.

Author_Institution

Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

Volume

7

Issue

6

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1339

Lastpage

1350

Abstract

The design of a chaotic neuron model is proposed and implemented in a CMOS very large scale integration (VLSI) chip. The transfer function of the neuron is defined as a piecewise linear (PWL) N-shaped function. In this paper, the new concept of the baseline function is introduced. It is the mapping of the neuron state to the neuron output. It is used to control the chaotic behavior of collective neurons. The chaotic behavior is analyzed and verified by Lyapunov exponents. An analog CMOS chip was designed to implement the theory and it was fabricated through the MOSIS program. The measurement diagnoses of the chip is demonstrated

Keywords

CMOS analogue integrated circuits; SPICE; VLSI; chaos; digital simulation; neural chips; CMOS VLSI chip; Lyapunov exponents; MOSIS program; analog CMOS chip; baseline function; chaotic neuron models; measurement diagnoses; piecewise linear N-shaped function; transfer function; Chaos; Circuit simulation; Differential equations; Neurons; SPICE; Semiconductor device measurement; Semiconductor device modeling; Switches; Transfer functions; Very large scale integration;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.548163

Filename

548163