Optimum voltage swing on on-chip and off-chip interconnect

Author

Svensson, Christer

Author_Institution

Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden

Volume

Issue

fYear

2001

fDate

7/1/2001 12:00:00 AM

Firstpage

1108

Lastpage

1112

Abstract

Reduced voltage swings are often used for saving power on interconnects. In this paper, we demonstrate the existence of an optimum voltage swing for minimum power consumption, for on-chip and off-chip interconnects. Actual values of optimum swings and corresponding power savings for high performance interconnects are estimated

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit interconnections; integrated circuit modelling; low-power electronics; high performance interconnects; minimum power consumption; offchip interconnect; onchip interconnect; optimum voltage swing; CMOS technology; Clocks; Energy consumption; Frequency; Integrated circuit interconnections; Inverters; Power amplifiers; Power system interconnection; Semiconductor device modeling; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.933468

Filename

933468

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1509850