Title :
Multi-Pattern
-Detection Stuck-At Test Sets for Delay Defect Coverage
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
6/1/2012 12:00:00 AM
Abstract :
An n-detection test set detects each target fault n times. A higher value of n increases the likelihood that defects around the site of a target fault will be detected. However, an n -detection test set that consists of single-pattern tests (generated for single stuck-at faults) cannot guarantee that delay defects will be detected. For this it is necessary to use multi-pattern tests. The procedure described in this work generates a multi-pattern n-detection test set for single stuck-at faults. The procedure is applied starting from a single-pattern n-detection test set for single stuck-at faults. Experimental results demonstrate that the multi-pattern n-detection test set achieves a high transition fault coverage. It achieves a similar bridging fault coverage to the single-pattern test set. An added advantage is that the multi-pattern test set typically requires significantly fewer clock cycles for test application than the single-pattern test set.
Keywords :
boundary scan testing; circuit testing; clocks; fault diagnosis; bridging fault coverage; clock cycles; delay defect coverage; delay defects; multipattern n-detection stuck-at test sets; multipattern test set; multipattern tests; n-detection test set detects; single stuck-at faults; single-pattern n-detection test set; single-pattern tests; target fault; transition fault coverage; Circuit faults; Clocks; Computational modeling; Delay; Fault detection; Integrated circuit modeling; Very large scale integration; $n$-detection test sets; Multi-pattern tests; scan circuits; stuck-at faults; transition faults;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2011.2144627