DocumentCode
1521264
Title
Effects of implant spacer on InP-based self-aligned pseudomorphic SIGFETs
Author
Chen, C.L. ; Mahoney, L.J. ; Calawa, S.D. ; Molvar, K.M.
Author_Institution
Lincoln Lab., MIT, Lexington, MA, USA
Volume
35
Issue
9
fYear
1999
fDate
4/29/1999 12:00:00 AM
Firstpage
746
Lastpage
748
Abstract
An InP-based normally-off superlattice-insulated-gate field-effect transistor (SIGFET) with a T-shaped gate structure has been developed using an angled self-aligned implant process. The spacing to the n source/drain regions created with this new process increases the breakdown voltage and lowers the gate capacitance. It also reduces the short channel effect while a high gm value is maintained. A cutoff frequency fT of 45 GHz was obtained for the SIGFET with 0.56 μm gate length
Keywords
III-V semiconductors; capacitance; indium compounds; insulated gate field effect transistors; ion implantation; semiconductor device breakdown; semiconductor device reliability; semiconductor superlattices; 0.56 micron; 45 GHz; InP; T-shaped gate structure; angled self-aligned implant process; breakdown voltage; cutoff frequency; gm value; gate capacitance; gate length; implant spacer; normally-off superlattice-insulated-gate field-effect transistor; self-aligned pseudomorphic SIGFETs; short channel effect; source/drain regions;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990380
Filename
769866
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