Offset in CMOS magnetotransistors. II. Reduction

For pt.I see ibid., vol.48, no.9, pp.1945-53 (2001). Offset reduction principles for complementary metal oxide semiconductor (CMOS) magnetotransistors (MTs) are discussed and several approaches are examined experimentally. Special emphasis is put on addressing the MT offset causes previously identified as most critical. Contributions from metal contact misalignment are suppressed by an improved emitter shape and metal contact position as well as by enhanced process control. Implantation angle effects are avoided by an orthogonal implant or are corrected for with the knowledge of the actual implant direction. Small scale effects from, for example, doping inhomogeneities or emitter-collector spacing mismatch are averaged out along an increased device edge length or in arrays of MTs. Emitter guard misalignment in suppressed-sidewall-injection-MTs (SSIMTs) is avoided by self-aligning the guard with poly-silicon mashing, MTs with average absolute values of offset below 0.14% between -40°C and +140°C are achieved. These offsets are equivalent to a magnetic induction below 4 mT at room temperature