Title :
A study of the threshold voltage variation for ultra-small bulk and SOI CMOS
Author :
Takeuchi, Kiyoshi ; Koh, Risho ; Mogami, Tohru
Author_Institution :
Silicon Syst. Res. Lab., NEC, Kanagawa, Japan
fDate :
9/1/2001 12:00:00 AM
Abstract :
This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (VTH) fluctuations. The impact of dopant-induced VTH variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be seriously degraded as the channel length approaches 25-30 nm even if an elaborate redundancy scheme is used. For the IC-SOI FETs, instead of the dopant fluctuations, silicon thickness variation is a critical issue. However, systematic simulation results show that, by optimizing the FET design, the thickness-induced VTH variations for both planar single gate and vertical double gate 25 mm IC-SOI FETs will be acceptable, assuming a reasonable thickness deviation range. Therefore, the IC-SOI CMOS is expected to be superior to the bulk counterpart at L=25 nm. It was also found that optimizing the back bias is necessary for suppressing the VTH variations of the single gate IC-SOI FETs
Keywords :
CMOS memory circuits; MOSFET; SRAM chips; silicon-on-insulator; IC-SOI FET; SRAM; back bias; intrinsic channel SOI CMOS; planar single gate device; redundancy; scalability; semiconductor doping; thickness control; threshold voltage fluctuations; ultra-small bulk CMOS; vertical double gate device; Circuits; Degradation; Doping; Double-gate FETs; Fluctuations; Impurities; MOSFETs; Random access memory; Silicon on insulator technology; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on