FPGA-based match filter implementation in frequency domain using an overlap-add method

In this research, a real time matched filter is implemented on FPGA using an overlap-add method. The matched filter that increases the signal-to-noise ratio (SNR) for pulse compression and low probability intercept (LPI) radars is implemented in digital domain. This design is implemented on Xilinx Virtex-5 based processing board that samples in intermediate frequency (2.5 GHz). In the overlap-add method, we propose to design the matched filter by using two parallel FFT cores. Furthermore, the matched filter results are presented for different intra-pulse modulations.