Title :
Application of interval analysis for circuit design
Author :
Leenaerts, D.M.W.
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
fDate :
6/1/1990 12:00:00 AM
Abstract :
In top-down circuit design, a principal task is to partition and map design constraints on a normal operating range of a collection of subblocks. This problem is propagated through each hierarchical level until the solutions for all levels are found. This top-down parameter assignment and instantiation of subblocks may eventually break down at some level due to an unrealizable circuit. Then the process has to be restarted a number of times before a realizable partition can be produced. An application of interval analysis in the design environment is presented to assure in advance that this process will always yield a solution. The presented methodology and corresponding algorithm can be used in hierarchical design strategies. At each hierarchical level, the solution space, if nonempty, is valid for all lower levels and is in agreement with decisions taken earlier in the hierarchy
Keywords :
circuit CAD; hierarchical systems; linear network synthesis; analogue IC; hierarchical design; interval analysis; subblocks; top-down circuit design; Algorithm design and analysis; Analog integrated circuits; Circuit analysis; Circuit synthesis; Design engineering; Equations; Integrated circuit interconnections; Operational amplifiers; Partitioning algorithms; Voltage;
Journal_Title :
Circuits and Systems, IEEE Transactions on