Electrical parametric and reliability of 5×50um TSVs for 3D IC

Author

Bhushan, Bharat ; Toh, Chin Hock ; Chan, Alvin ; Ow, Isaac ; Wong, Loke Yuen ; Barman, Arkajit Roy ; Sudheeran, Shalina ; Rao, Chethan ; Abdul, Wahab Mohammed ; Chew, Jason ; Vijayen, Jay ; Mahajan, Uday ; Ericson, David ; Kumar, Narendra ; Ramaswami, Ses

Author_Institution

Silicon Syst. Group, Appl. Mater. Inc., Albany, NY, USA

fYear

2014

fDate

20-23 May 2014

Firstpage

363

Lastpage

366

Abstract

We present electrical parametric and reliability of 5×50um through silicon vias (TSVs) for three dimensional integrated circuits (3D IC). Electrical parameters such as oxide breakdown voltage (V_bd^TSV), leakage current (I_leak^TSV), oxide capacitance (C_ox^TSV), dielectric constant (k), minimum capacitance (C_min^TSV), threshold voltage (V_th) and mobile oxide charges (Q_m) of blind TSVs are analyzed. And, the reliability of TSVs is analyzed with thermal cycling between -55°C to 125°C with a dwell time of 10-15 minutes by following JEDEC standard No. 22-A104D.

Keywords

capacitance; electric breakdown; integrated circuit reliability; leakage currents; permittivity; three-dimensional integrated circuits; 3D integrated circuit; JEDEC standard No. 22-A104D; TSV; dielectric constant; electrical parameter; integrated circuit reliability; leakage current; minimum capacitance; mobile oxide charge; oxide breakdown voltage; oxide capacitance; size 5 mum; size 50 mum; temperature -55 C to 125 C; thermal cycling; three-dimensional integrated circuit; threshold voltage; through silicon via; Capacitance; Leakage currents; Reliability; Silicon; Thermal analysis; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831835

Filename

6831835