Abstract :
The 2010 IEEE Journal of Solid-State Circuits Best paper award was given to "An 18 b 12.5 MS/s ADC with 93 dB SNR," by Christopher Peter Hurrell, Colin Lyden, David Laing, Derek Hummerston, and Mark Vickery, published in IEEE Journal of Solid- State Circuits (JSSC), vol. 45, no. 12, pp. 2647??2654, December 2010. According to JSSC Editor-in-Chief Un-Ku Moon, this work was judged the best in JSSC 2010 because "it sets a new performance benchmark for high-resolution CMOS converters, showing a measured SNR of 93 dB at a sampling rate of 12.5 MS/s. Hurrell et al. achieve this level of performance by pipelining two multibit successive approximation converters via a highgain residue amplifier. Through this architectural partition, the presented ADC judiciously unites favorable analog design capabilities and digital enhancements such as weight calibration, redundancy, and dither. The end result is a substantial advancement of the state of the art that stands out in a publication space that is dominated by less intimidating low-to-moderate precision designs."
