• DocumentCode
    154197
  • Title

    ESD characterization and design guidelines for interconnects in 28nm CMOS

  • Author

    Zongyu Dong ; Fei Lu ; Li Wang ; Rui Ma ; Chen Zhang ; Hui Zhao ; Wang, Aiping ; ShiJie Wen ; Wong, Rita ; Fung, Rita ; Chu, Chris ; Watt, Jeremy ; Jahanzeb, Agha ; Liaw, Peter

  • Author_Institution
    Dept. of EE, Univ. of California, Riverside, Riverside, CA, USA
  • fYear
    2014
  • fDate
    20-23 May 2014
  • Firstpage
    99
  • Lastpage
    102
  • Abstract
    This paper reports comprehensive transient electrostatic discharge (ESD) characterization of backend interconnects in a foundry 28nm CMOS. Testing results reveal details on metal current handling capability and on-chip ESD protection ability. ESD design guidelines for interconnects are provided for chip-level ESD protection circuit designs in 28nm CMOS.
  • Keywords
    CMOS integrated circuits; electrostatic discharge; integrated circuit interconnections; CMOS; ESD characterization; ESD design; backend interconnects; chip-level ESD protection circuit designs; electrostatic discharge characterization; metal current handling capability; on-chip ESD protection; size 28 nm; Circuit synthesis; Electrostatic discharges; Foundries; Integrated circuit interconnections; Metals; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4799-5016-4
  • Type

    conf

  • DOI
    10.1109/IITC.2014.6831845
  • Filename
    6831845
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=154197