Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Author

Wafula, Fred ; Pattanaik, Gyanaranjan ; Enloe, Jack ; Hummler, Klaus ; Sapp, Brian

Author_Institution

Atotech USA Inc., Albany, NY, USA

fYear

2014

fDate

20-23 May 2014

Firstpage

143

Lastpage

146

Abstract

In this paper, physical and electrical results of full wafer direct Cu plating of 2×40 μm TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech´s TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed.

Keywords

copper; electric breakdown; electroplating; integrated circuit reliability; integrated circuit testing; ruthenium; three-dimensional integrated circuits; Atotech TSV III chemistry; Cu; Ru; TSV; bottom-up growth; full wafer direct plating; high aspect ratio through silicon vias; in-line electrical test; physical vapor deposition; plating nonuniformity improvement; sidewall suppression; size 300 mm; structured wafer; void free fill; voltage ramp dielectric breakdown reliability testing; Breakdown voltage; Chemistry; Films; Resistance; Semiconductor device reliability; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831848

Filename

6831848