Title :
Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology
Author :
Rabie, Mohamed A. ; Premachandran, C.S. ; Ranjan, Rajiv ; Natarajan, Mahadevan Iyer ; Sing Fui Yap ; Smith, D. ; Thangaraju, Sara ; Alapati, Ramakanth ; Benistant, F.
Author_Institution :
GLOBALFOUNDRIES Inc., Malta, NY, USA
Abstract :
For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3 ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; three-dimensional integrated circuits; PMD oxide; contact protection layer; keep out zone process development; middle of line layer stack; planar CMOS technology; size 20 nm; via middle TSV; Annealing; Copper; Silicon; Tensile stress; Threshold voltage; Through-silicon vias;
Conference_Titel :
Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-5016-4
DOI :
10.1109/IITC.2014.6831870
