Design and implementation of an RSFQ switching node for petaflops networks

This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW.